A Sequence Pair-Based Non-Slicing Floorplanner for Uncertain Designs

Floorplanning is an important step in an early phase of VLSI design. For faster design convergence, there is an urgent need to start floorplanning as early as possible, even when not all modules are designed. Therefore, it is desirable to consider floorplanning with uncertainty to obtain a compact and reliable floorplan when the dimensions and interconnections of modules are not fully determined. In this paper, we propose a sequence-pair based floorplanner for uncertain designs. We first derive a probability-based longest path algorithm for a constraint graph to evaluate the enclosing width and height distributions. We then use simulated annealing to minimize the expected value and the variance of the enclosing area. Our floorplanner with uncertain data can consider non-slicing floorplans and interconnection cost which are not addressed before, and can generate a reliable and compact floorplan. Experimental results show that with 10%–30% uncertainty we have 98% confidence that the area derivation is within only 2% and the average dead space is less than 7%.